HDLC

The HDLC Protocol Controller can be used as a D-channel interface in a digital line card comprised of multiple DNICs.

HDLC协议控制芯片也可以作为D通道接口，用在包含多个DNIC的数字线路卡上；

This literary adopt a High-level Data Link Control protocol ( HDLC) which faces bit, choose the serial communication controller in conformity with it, make HDLC realized conveniently through initializing the hardware.

本文采用面向比特的高级数据链路控制规程，并选择了与之相适应的串行通信控制器，使HDLC可通过硬件的初始化方便地实现。

HDLC is a high level data link control protocol. It's function can be realized by special HDLC processor or FPGA.

HDLC（高级数据链路控制）协议的功能可由专用的HDLC处理芯片或FPGA（现场可编程门阵列）实现。

The plasma levels of HDLC were differed significantly between the TT genotype and the CC genotype ( P < 0.001) in CHD group.

在冠心病组中，TT基因型血浆高密度脂蛋白胆固醇水平明显低于CC基因型（P

Result: The levels of TC, TG, LDL-C, VLDL-C and TC/ HDLC were decreased significantly in serum of ASO rabbits.

结果：通心络胶囊明显降低动脉粥样硬化闭塞症家兔血清TC，TG，LDL-C，VLDL-C水平及TC/HDL-C；

The second part uses FPGA ( Field Programmable Gate Array) to realize the HDLC protocol.

第二部分是利用FPGA（Field Programmable Gate Array，现场可编程门阵列）来实现HDLC协议。

Methods: TC, TG, HDL C, LDL C, blood glucose ( BG ) and EKG were determined in 906 elderly persons.

方法　采用 标准化 方法测定血清总胆固醇(TC) 、 甘油三脂(TG) 、 高密度蛋白胆固醇(HDLC) 、 低密度脂蛋白胆固醇(LDLC) 、 血糖 ( BG ) 水平,与常规12导联心电图比较分析.

in reliable protocols such as tcp and hdlc, a timer is required to timing for data package overtime retransmission.

在TCP、HDLC等能提供可靠通信服务的通信协议中，需要使用定时器来对数据包的超时重发进行计时。

Design of E1/ T1 Interface module for HDLC

HDLC通信E1/T1接口模块设计

Apo E3/ 4 genotype had significantly higher serum total cholesterol ( TC), LDL-cholesterol ( LDLC) and apo B levels and lower HDL-cholesterol ( HDLC) level compared to apo E3/ 3 and apo E2/ 3 genotypes in the patients and in the controls.

与E3/3及E2/3基因型比较，E3/4基因型者有较高的总胆固醇、低密度脂蛋白胆固醇和载脂蛋白B水平及较低的高密度脂蛋白胆固醇水平。

Results: TFBL remarkably reduced LDL C and serum glucose, raised HDL C, improved lipid metabolic disorder and glucose tolerance.

结果：TFBL能明显降低高脂血症和糖尿病大鼠的血清LDLC，升高HDLC，降低血糖，改善糖耐量。

Half duplex ( HDX). FDX-normal response mode and FDX-asynchronous response mode of HDLC respectively is simulated. The results of simulation are analysed and illustrated.

HDLC半双工（HDX）、全双工正常响应方式（FDX-NRM）和全双工异步响应方式（FDX-ARM）的模拟。

Study on the Applications of 82530 Chip-Based HDLC/ SDLC Protocol High Speed Digital Communications

基于82530芯片的HDLC/SDLC规程高速数字通信应用的研究