sampling clock的例句大全

Secondly, the effects of carrier frequency offset, sampling clock offset, and symbol timing offset on OFDM signals are exploited.

其次本文分析了符号定时误差、采样时钟偏差、频率偏差对解调信号的影响。针对符号定时同步问题，阐述了利用OFDM帧头训练序列同步的方法；

This thesis analyzes some influences on the performances of OFDM digital communications, which include carrier frequency offset, symbol timing offset and sampling clock offset.

分析了载波频率偏差、符号定时偏差和样值频率偏差对OFDM系统性能的影响。

Interpolation theory in digital signal processing has application in timing synchronization, which makes the sampling clock independent of the timing control so that timing adjustment is realized completely through digital disposal. The issue of interpolation in timing synchronization is discussed.

论文探讨了数字信号处理中插值理论在定时同步中的应用，它使得接收端的采样时钟独立于定时控制，定时调整完全通过数字处理方法得以实现。

joint estimation of sampling clock and residual frequency offset of ofdm system based on discrete preamble

OFDM系统中离散导频的采样钟和残留频偏联合估计算法

pixel clock output frequencies range from 10mhz to 140mhz with sampling clock jitter of 250ps peak to peak.

像素时钟输出频率范围从10MHz到140MHz的采样250ps的峰峰值抖动。

the adc aperture jitter must be minimal, and the sampling clock generated from a low phase-noise quartz crystal oscillator.

ADC的孔径抖动必需尽可能的小，而且要使用低相位噪声的石英晶体振荡器作为采样时钟发生器。

Following the introduction of the basic principle of OFDM, some nonideal effects on the performance of OFDM systems are discussed, such as carrier frequency offset, symbol timing offset and sampling clock deviation.

本文在简要介绍了OFDM的基本原理、关键技术的基础上，针对同步问题进行了深入研究。首先分析了同步偏差中的频率偏差、符号定时偏差及采样时钟偏差对系统性能的影响。

Of course the sampling clock is itself a digital signal.

时钟本身也是数字信号,也会干扰模拟电路.

the sampling clock generator must also have adequate spectral purity.

时钟发生电路固有的抖动应该足够小.

Design of High Accuracy Synchronous Sampling Clock in Digital Substations

数字化变电站中高精度同步采样时钟的设计

Because of the capacitance bottom plate sampling and fully differential structure, the charge injection effect of switched-MOSFET and the clock feed-through effect induced signal error are eliminated. The linearity, signal to noise ratio ( SNR) and conversion-speed of the ADC are improved.

由于采用了电容下极板采样和全差分结构，能够有效地消除开关管的电荷注入效应和时钟馈通效应引起的采样信号的误差，提高模数转换器的线型度、信噪比和转换速度。

Application of the technology of sampling in different phase in clock circuit realizes maximum 200M equivalent sampling rate of timing analyzer.

在时钟电路中采用分相采样技术，实现了定时分析最高200M的等效采样速率。

Because the same master clock is used in sampling circuit, phase alignment isn't needed, and the circuit design can be simplified.

由于采用同一主时钟对数据抽样，不需要进行相位校准，简化了电路的设计；

New method for accurate measurement of clock jitter based on equivalent? time sampling

基于等效采样时钟jitter的精确测量

The difference clock delay match technology adjusts the two channel AD analog clock phase and implements the two way AD uniformly-space sampling.

差分时钟延迟匹配技术通过对两路AD的采样时钟进行相位调整，实现了两路AD的等间隔采样。

We also use the bootstrap circuit to boost the clock of NMOS sampling switch.

芯片还采用了自举电路对时钟信号进行提升,使得NMOS采样开关 的栅电压跟随输入信号变化.

Owing to GPS clock, which has no accumulative error, and quartz oscillator, which is very stable, the time counting value is obtained without delay via hardware by combining high speed sampling and PPS ( Pulse Per-Second)-snapping.

利用GPS时钟无累计误差和高精度晶振频率稳定性高的特点，并将高速采样与秒脉冲捕捉有机结合，通过硬件方式无延时地捕捉秒脉冲以获取精确的时间计数值。

Presented the principle of large screen field emission display integrated system based on FPGA control technology which includes the video sampling module, buffer module, clock control module, integrated gray-modulation control module and the integrated row control module.

论述基于FPGA的FED视频驱动显示控制系统的工作原理，包括了视频采集控制模块、缓存模块、时钟控制模块、集成灰度调制控制模块以及行集成控制模块等的FPGA控制技术。

in gps sampling unit a highly precise clock is used to record the accurate arrival time of traveling wave, which is developed on the basis of a method for supervising and correcting gps clock in real time.

GPS采样单元采用了以GPS时钟的在线监测与修正方法研制而成的高精度时钟发生装置，实现行波波头到达时刻的精确记录。