Verilog的例句大全

Research fingerprint recognition algorithm IP core in Verilog HDL ( hardware description language).

研究基于Verilog hdl（硬件描述语言）的指纹识别算法IP核。

In this paper, the semantics of Verilog program are studied in a discrete continuous hybrid time model, a hybrid interval is denoted as the description of a run of Verilog program.

在连续离散混合时间模型中考虑Verilog的语义行为，将混合模型中的一个区间作为Verilog程序一次运行过程的指称。

Finally, on the Verilog implementation of FIR filters, a new structure is presented, with which the speed of the filters are twice the speed with the distributed algorithms.

最后针对FIR滤波器的Verilog实现，提出了一种新型的并串结构，使得滤波器的处理速度是分布式算法的两倍。

The Verilog HDL which is understood easily is adopted for the paper.

系统采用一种软件硬化的设计思路，应用了Verilog hdl硬件语言，该语言较容易理解。

Our method has advantage in its fine grain, without ( writing-style) ( limitation) ( and) in dealing with more Verilog components characteristics.

与以前的方法相比，该方法的优点是细粒度的、不受书写格式的限制，并且能处理更多Verilog的语法元素。

This article has analyzed the development of real-time image processing system, FPGA technology development present situation, EDA technology characteristic, its development phase and the circuit design flow, Verilog HDL, FPGA/ CPLD characteristic, its programming technology, the structure and the development flow.

本文以实际开发嵌入式系统的流程作为组织文章，布局谋篇的线索。本文分析了实时图像信号处理系统的发展状况，FPGA技术的发展现状。EDA技术特征、发展阶段、电路设计流程；

Detailed introduction data acquisition software realization storage module, namely the key in this paper is an SRAM, reading and writing Verilog HDL realized.

详细介绍数据采集存储模块软件实现是本文的重点，即SRAM读写的Verilog hdl实现。

Combined with the receiver circuit of SDH network analyzer, transmitter circuit is simulated by NC-VERILOG simulation tools, traversing a variety of TEST_CASE for simulation.

论文构建了具有HARNESS结构的仿真测试平台，利用NC-VERILOG工具，结合SDH网络分析仪接收端电路，对发送端电路进行联合RTL仿真。

We choose a subset of Verilog for our research, which hold the key features of Verilog, including event control, time delay, and concurrency.

选择了Verilog的一个子集作为研究对象，该子集包括了Verilog最重要的语言特征，如事件控制，时延，并发性等；

High Level Design Environment for Digital Integrated Circuit Based on Verilog HDL

基于Verilog HDL的数字集成电路高层设计环境

then two kinds of algorithms are implemented on fpga using verilog-hdl language abided by top-down design rules, furthermore, their functions are verified and their performance are analysed.

然后在FPGA上采用TOP-DOWN的设计思想，将这两种算法用Verilog-HDL语言分别实现，并进行了功能验证和可行性分析。

the rtl design of the module is completed using verilog.

针对该芯片的架构，提出了缓冲器管理单元的设计方案，并应用Verilog语言完成了该单元的RTL级设计。

Manchester codec Verilog code very good speed, but also occupy less resources.

曼彻斯特编解码Verilog代码非常好的速度快, 而且资源占用少.

Verilog HDL design of frequency divider in RTC module is studied here.

文中研究在RTC模块中分频器设计的VerilogHDL实现.

In Verilog HDL code , division is improved by quantizing the divisor, which makes hardware realization easy.

在描述硬件过程中,论文对算法中的除法运算进行改进,将除数进行量化处理, 使其更易于硬件实现.

The function of circuit was verified by Verilog-XL.

整个电路的功能通过了Verilog-XL 的仿真.

UART Receiver Verilog Code complete code can be used directly.

异步接收器Verilog代码完整的源代码可以直接使用.

Research and Realization of Digital Image Sharpening Based on Verilog

基于Verilog的数字图像锐化研究和实现

This paper presents an automatic model compiler, CAMC, which accepts device models in behavioral language, such as Verilog-AMS, and generates C code according to standard circuit simulator programming interface.

本文实现了一个自动化的模型编译器CAMC。CAMC能够接受使用Verilog-AMS等行为级语言描述的器件模型，并按照标准电路仿真器的接口产生C语言代码。