circuits的例句大全

Cracking study on the flexible circuits under uniaxial tensile strain

轴向应变导致柔性电路的裂化研究

Then functions, control ways, hardware circuits and software process of the VAV terminal controller are analyzed in detail.

具体分析了此系统的VAV末端控制器的功能、控制方式、硬件电路和软件流程。

All the circuits in digital terminal module are designed in FPGA.

除A/D采样以外，终端部分的全部电路均在FPGA中实现。

Circuits for signal collection have been given to measure the stator terminal voltage and current value.

同时也设计了信号采集电路，用于测量控制系统所需的三个定子端电压信号和相电流反馈信号。

Based on this theory, the current-mode CMOS circuits realizing ternary addition and ternary multiplication operations are designed.

基于该理论，本文设计了实现三值加法和三值乘法的电流型CMOS电路。

Realization of Ternary Arithmetic Circuits by Using Current-Mode CMOS Circuits

用电流型CMOS电路实现三值算术电路

Design of ternary arithmetic circuits based upon uh-gates

基于U h门的三值算术电路设计

An Investigation into I~ 2L Ternary Logic Circuits

I~2L三值逻辑电路的研究

Symmetric ternary logic and symmetric ternary CMOS circuits

对称三值逻辑及对称三值CMOS电路

The four key problems, i.e., the design of injection node, the realization of fault injection circuits, the design of the structure of the fault injection tool and the software package of the intelligent BIT test adapter, are mainly discussed.

对智能化测试适配器故障注入节点的设计、故障注入电路的实现、故障注入器结构体系的设计、智能化测试适配器软件包四个关键技术问题给出了具体的方案。

The test failure control proposed is also applicable for the other fields of integrated circuits and discrete devices.

本论文提出的测试失效控制方法同样适用于其它集成电路及分立器件测试领域。

The Military Thick-film Hybrid Integrated Circuits Analysis of the Unqualified Reason and Control Methods of PIND Test Failure

军用厚膜混合集成电路PIND试验不合格原因分析及控制方法

Test Generation Algorithm Based on Search State Dominance for Combinational Circuits

基于搜索状态控制的组合电路测试生成算法

Research on BDD and Its Applications to Circuits Test Generation and Reliability

BDD及其在电路故障检测与可靠度中的应用研究

A Method of Test Generation for Large Combinational Circuits Using Input Vector in Three

用三矢量链对大规模组合电路的测试生成研究

With testing the method with 10 benchmark circuits, the result is good for low test pattern length, high fault coverage and high efficiency.

该系统运行10个Benchmark电路，取得了低测试长度、高故障覆盖、高效率的良好效果。

In this paper, based on the build-in self-test for logic circuits, a new approach is proposed to reduce pseudorandom test sequence length.

本文建立在逻辑电路内部自测试的基础上，提出了一种新的缩短伪随机测试序列长度的方法。

The multiple-valued instrument made according to the proposed design can not only produce multiple-valued function signal, but also can test the logic level of multiple-valued logic circuits and analysis the logic function of c circuits.

根据设计的多值仪器不仅能产生多值函数信号，还可以测试多值逻辑电路的逻辑电平，分析多值逻辑电路的逻辑功能。

Research on Test Technology of Combinational Logic Circuits in the Control System of Magnetic Bearings

磁力轴承控制系统中组合电路测试技术研究

Study on Chaos Control and Chaotic Optimization with Its Applications in Test Generation for Combinational Logic Circuits

混沌控制与混沌优化及其在组合电路测试生成中的应用研究