frequency divider的例句大全

The key building blocks in the frequency synthesizer are-controlled oscillator ( VCO ) and high frequency divider circuit.

压 控振荡器 与除频器是频率合成器电路中,主要的电路之一.

Design and precision analysis of dual-modules frequency divider with regulable duty ratio

一种可调占空比型双模分频器设计及精度分析

A modulator reduces the quantization error of the frequency divider.

调制器减少该分频器的量化误差.

Verilog HDL design of frequency divider in RTC module is studied here.

文中研究在RTC模块中分频器设计的VerilogHDL实现.

The digital part includes closed loop oscillator, frequency divider, combinational logic circuit, non-overlapping clock generation circuit.

数字部分包含环形振荡器、分频器、组合逻辑门、非交叠时钟产生电路。

The Design and Application of Decimal Fraction Frequency Divider

小数分频器的设计及其应用

In addition, fractional frequency divider has greatly reduced error in baud rate.

另外，采用小数分频等技术极大地降低了串口的波特率误差。

High Speed AlGaAs/ GaAs HBT D-Type Flip Flop and Static Frequency Divider

高速AlGaAs/GaAs HBT D-触发器和静态分频器

The circuit design, fabrication, and performance of high-speed AlGaAs/ GaAs HBT D-type flip flop and static frequency divider integrated circuits are described.

叙述了高速AlGaAs/GaAs HBT D-触发器和静态分频器的设计、制造和性能。

N is the desired noninteger frequency divider.

n为所要求的非整数分频值。

Abstract The on-wafer testing system with microwave probe has been made and used to test the GaAs high-speed dynamic frequency divider chips on wafer.

本文研制出多触头微波探针，建立了微波探针在片检测系统.针对GaAs高速集成电路&动态分频器电路芯片进行了在片测试和筛选。

Design and Realization of Frequency Divider in Servo Drivers Based on FPGA

基于FPGA的伺服驱动器分周比设计与实现

The analysis of spike pulse noise rejection, frequency divider and dead time in oscillator and control circuit;

振荡器和控制电路中尖峰脉冲噪声抑制、两分频电路及死区时间设定；

this system uses the quartz crystal oscillator, the frequency divider, the counter, the monitor and the timing electric circuit composition.

本系统采用石英晶体振荡器、分频器、计数器、显示器和校时电路组成。

preliminary inquiry of implementation of zero phase shift for frequency divider

分频器实现零相移的初步探讨

a high-speed toggle flip-flop ( tff) based frequency divider is presented, which outputs two channels of orthogonal signals, i and q, with dynamic load.

给出了一个电源电压为1.8V、功耗为0.9mW的4.8GHz二分频器。该分频器采用基于反转触发器（TFF）的电路结构，使用动态负载，输出I、Q两路正交信号。

It was used as a frequency divider and no numbers are decoded from it.

它被用作无解码输出的分频器.

Relation between-3 dB frequency and risetime for resistive voltage divider

电阻分压器-3dB频率与上升时间的关系

A novel design plan of divider was presented. In the higher frequency band, M/ S DFF structured by CMOS SCL was used to divide to satisfy the high speed command.

提出了一种新颖的分频器设计方案，在高频段采用改进的CMOS源耦合逻辑（SCL）结构的主从D触发器进行分频，以满足高速要求；

Applications of digital system design about LPM database 、 divider and DDS frequency synthesizer in the MAX + PLUSare introduced.

介绍了MAX+PLUS 中LPM库车 RAM、除法器和DDS频率合成器上进行数字系统设计的应用.