instruction cache的例句大全

A Low-Power Instruction Cache Design Based on Record Buffer

基于记录缓冲的低功耗指令Cache方案

shopping list a mini instruction cache in a general purpose dsp

一种通用DSP单端口指令Cache设计

In this paper, the instruction FIFO in the SDRAM controller is introduced. Full utilized the pipeline characteristic of the SDRAM, the performance of the no cache embedded microprocessor is improved.

本文提出了SDRAM预取FIFO的设计，充分利用SDRAM的流水特性，提高无Cache嵌入式处理器性能。

Modern microprocessors which use Cache memory system and instruction pre-fetching increase the difficulty to compute the upper bound accurately.

由于现代微处理器使用了基于Cache存储和指令预取技术，增加了准确确定这一上界的难度，为此提出了一种基于指令Cache和指令预取联合模型的嵌入式软件性能评估新方法。

This paper presents the principal features of Intel's Pentium Architecture. It includes the description of basic blocks, pipeline structure, instruction pairing rule, floating point unit, on-chip caches and TLBs and the cache consistency protocol for supporting multiprocessing systems.

本文介绍Intel最新产品Pentium体系结构的主要特点，包括它的部件组成、流水线结构、指令配对法则、浮点部件、片上cache与TLB以及支持多机系统的cache一致性协议。

high performance instruction set simulator using dynamic decode cache

采用动态译码缓存的高速指令集模拟器