level logic circuit的例句大全

Investigation into Ternary GaAs Logic Level Circuit s

三值GaAs逻辑级电路的研究

This kind of function fine tri-state logic indicating circuit is composed of 555 integrate timer, logical level threshold value adjustment circuit and the logic indicating circuit.

这种功能优良的三态逻辑指示电路由555IC集成定时器、逻辑电平阈值调节设定电路、逻辑指示电路构成。

Graph approach for logic circuit input is adopted by the DCLSS, device model is based on five-value, three-strength, and up/ down-jump delay model, simulation algorithm is on table-event method, time-mapping technique, and hybrid simulation of gate and function block level.

软件采用图形输入方式，元件模型为五值、三强度及上下跳变延迟，模拟算法采用表驱动方法、时间映射方式、门级和功能级混合模拟。

Logic Circuit Level Design by Using MDS Diagram& "A 30's basketball Timer" Design

应用MDS图的逻辑电路级设计&篮球30秒定时计时器的设计

A Simplified Design of a Mixed Level I~ 2L Three Valued Logic Circuit

混合级I~2L三值逻辑电路的简化设计

The level of complexity in testing the designed logic circuit and system.

对所设计的逻辑电路和系统进行故障测试的难易程度.