memory bus的例句大全

A data memory unit based on USB bus with big capacity is designed for data storage.

设计了基于USB总线的大容量数据存储模块。

In data storage transmission modular, we adopt PCI bus line and FIFO data memory carry out succession for plenty of data to storage transmission, guarantee AE signal accurate collecting.

数据存储传输模块采用PCI总线和FIFO数据存储器对大量的数据进行连续存储传输，保证数据的准确完整。

The platform consists of AMBA on-chip bus models, RISC CPU model and memory module.

平台主要包括基于AMBA规范的总线模型、RISC CPU模型和存储器模型。通过GUI可以进行设计仿真。

Hardware part includes GPS modules, CDMA module, CAN bus communication module, memory module, communication interface module, power management module and the MCU peripheral circuit module.

硬件部分包括GPS模块、CDMA模块、CAN总线通信模块、存储模块、通信接口模块、电源管理模块及MCU的外围硬件电路模块。

the design of main circuit includes system startup and reset, memory assignment and management, interrupt response and management, external bus interface, clock and power control, system development and debugging function.

其中，主体电路设计部分包括了系统启动与复位、内存分配与管理、中断响应与处理、外部总线接口、时钟与电源管理、系统开发与调试功能等内容；

the data memory access was implemented by bus duplicated using tristate bidirectional gate;

采用三态双向门电路控制存储器模块总线复用实现数据访问；

each pod has its own processors and memory, and is connected to the larger system through a cache-coherent interconnect bus.

每个pod具有自己的处理器和内存，并通过一条高速缓存一致性互连总线（cache-coherentinterconnectbus）连接到较大的系统。

The address bus specifies the memory locations ( addresses ) for the data transfers.

地址总线为数据传输指明内存位置 ( 地址 ).

A memory map is the addressing plan for the address bus bits.

存贮器布局就是地址总线各位的寻址平面图.

A 32 bit address bus can locate 4 Gigas ( 2 ^ 32 ) of different memory locations.

32位地址总线可以确定4G ( 2的32次幂 ) 个不同的存储位置.

Address Bus: Locates data stores in the memory, input port, or output port.

地址总线: 确定数据在存储器, 输入口或输出口中的存储位置.

There will be a separate data bus connecting the central processing unit memory devices.

一种由四个独立的接收-发送器组合而成的部件,设计用于双向总线系统,如用在数据总线中.

There will be a separate data bus connecting the central processing unit to memory devices.

有一条独立的数据总线将中央处理机与存储器连接起来.

The SSR is based on NAND FLASH memory, with bus-width expansion and pipeline technique.

存储器基于NAND型FLASH芯片, 采用并行扩展及流水线操作的技术.

Bus is a microprocessor and memory computer chips and communications equipment with connecting hardware channel.

总线是将计算机微处理器与内存芯片以及与之通信的设备连接起来的硬件通道.

Design of Compatible Memory Controller Based on WISHBONE Bus

基于WISHBONE的可兼容存储器控制器设计

He demonstrated this model how to detect processor is used, bus line conflict and memory file.

他演示了该模子若何检测措置器操纵 、 总线冲突及存储文件.

Integrally, the RISC CPU has BIU ( Bus Interfacing Unit), IDU ( Instruction Decoding Unit)-. ALU ( Arithmatic& logic Unit), MMU ( Memory Management Unit) etc.

从整体方面来说，整个微处理器大致分为BIU（总线接口单元）、IDU（指令译码单元）、ALU（算术逻辑单元）、MMU（存储管理单元）等等。

A New FERA Bus Drive and Memory Module for High Speed Data Acquisition System

用于高速数据获取系统中的FERA总线驱动和存储器部件

Your write system call will be interrupted by the bus error signal SIGBUS, because you performed a bad memory access.

此时write系统调用会被进程接收到的SIGBUS信号中断，因为当前进程访问了非法内存地址。