parallel memory的例句大全

it maps a 2-d logic space onto physical parallel memory modules.

该存储系统完成了二维逻辑空间到物理空间上并行存储器模块的映射。

In this paper the relationship between memory contention and ( a, M), the greatest common divisor of a and M, is investigated, where M is the number of parallel memory modules, and a is a constant increment of address.

本文论述了以增量a（常数）访问M个体组成的并行存储器时，存取碰头和（a，M）的关系，这里（a，M）表示a和M的最大公因数。

Thirdly, based on the consideration of improving the utilizing efficiency of off-chip bandwidth, we have designed and implemented a data-parallel memory system for our Tiled Stream Processor in current project.

从提高片外带宽使用率的角度出发，设计和实现了分片式流处理器的数据并行存储系统。

A Parallel Memory Cache System and Its Implementation

一种并行内存缓冲系统及其实现技术

in massive parallel distributed shared memory multiprocessor, maximum reducing the remote memory access latencies is the key of improving the whole system performance.

在大规模并行分布式共享主存多处理机系统中，尽可能减少系统中远程访问时延，是提高系统整体性能的关键。

Implementation of A low memory and high speed parallel wavelet transform based on FPGA

一种低存储高速并行小波变换算法的FPGA实现

Then, we design and implement a Shared by Heterogeneity Processor L2 Cache sub-system to exploit the extra parallelism and locality in stream application, and improve the off-chip memory bandwidth. These lead to a more completed parallel hierarchy stream memory system.

针对流应用中各种可用的并行性和局域性，我们设计并实现了由异构处理器共享的二级缓存子系统，并对片外存储层次进行改进，完善了原有的存储层次结构。

The paper introduced FDU ID memory of 408 seismograph and a device using a bi-directional parallel port for printer on a personal computer to read/ write FDU EEPROM chip.

本文介绍408地震仪FDU标识号存储器及一款利用个人计算机双向并行打印口读写FDU EEPROM芯片的装置。

BUFFER CAPACITY Experimental study of optical parallel cache memory arrays

光学并行高速缓冲存储列阵的实验研究

Technique of Parallel Interface with External Memory Using MOTOROLA Microprocessor

无数据地址总线端口的MOTOROLA系列单片机与外部存储器的并行接口技术

Application of memory information saving to master slave parallel OS

内存现场保护技术在主从式并行OS中的应用

Electrically erasable programmable read-only memory ( EEPROM) is mainly applied to information memory such as intelligentized IC card, single chip microcomputer, etc. It is divided into parallel and serial.

电可擦除可编程只读存储器（EEPROM）主要应用于智能IC卡，微型计算机等各种需要对信息存取的场合。EEPROM分为并行和串行两种。

Based on the control strategy to a hierarchical and distributed network databaSe, a design scheme combined internal memory with external memory and supported by parallel microcomputer system is proposed.

基于一种层次化、分布式网络数据库的控制策略，提出了一种由并行处理机系统支持的、内存和外存结合式的数据库实现方案。

Research of Fast Commit and Highly Efficient Recovery Method for Parallel Main Memory Database

并行内存数据库快速事务提交与高效恢复方法研究

We implement layered caching mechanism ( global disk caching and memory caching) using dynamic sharing running memory buffer algorithm to support more stable and real-time parallel streams;

采用动态共享运行缓冲区算法实现了分层缓存机制（全局磁盘缓存和内存缓存）以支持更多稳定、实时的并发流；

Block ADI Algorithm on Massively Parallel Processing System with Distributed Memory

适合在分布存储大规模并行处理系统上应用的块ADI算法

The new avionics system contains highly synthetic sensors, parallel processors and shared memory with high levels of integration. Served as standard of data communications in many military environments, MIL-STD-1553B can not satisfy the need of modern systems.

新一代的航空电子系统中包含了高度综合的传感器、并行处理器和共享存储器，以MIL-STD-1553B为代表的现用的航电数据总线已经不能够满足现在的系统对数据传输的要求。

Many application systems use plug-in equipment to collect data an(?) data is transmitted directly to the memory of the computer. But data acquisition car(?) and PC are divided in some application systems and it can only be connected to PC through parallel or serial interface.

许多应用系统使用插入式设备采集数据并把数据直接传送到计算机内存中，而某些应用系统中数据采集卡和PC分离，只通过并行或串行接口和PC相连。

parallel access to multiple memory banks by several data buses and dual access through dual access random access memory ( daram) reduces the memory bandwidth limit.

充分利用CPU多条数据总线并行访问多个存储器块的能力和双端口存储器（DARAM）一个周期两次访问的能力，减小存储器带宽的限制。

in the first stage, the amplitude sequence of modulating signal is generated by addressing waveform memory and added by the frequency value of carrier wave in the adder. the parallel output of the adder is served as the frequency control word of the second phase accumulator.

在第一级寻址结构中产生的调制信号幅度序列和载波频率值在加法器中相加，并将相加的结果作为第二级相位累加器的频率控制字；