parallel multiplier的例句大全

A parallel multiplier configuration especially suitable for VLSI realization is presented.

用简化部分积的扩展符号位所在全加器的连接的方法提出了一种适于VLSI实现的并行乘法器结构。

Design and implementation of parallel multiplier used in the surround sound processing ASIC

环绕立体声处理ASIC中并行乘法器的设计与实现

a new high regular structure of partial parallel multiplier for irreducible trinomial generated finite field is proposed.

提出了一类新的具有高度规则性的部分并行三项式有限域乘法器架构。

By selecting the bit parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion, the widely used RS decoder is constructed.

采用了一种可以避免求逆运算的修正BM迭代算法，并且利用这样的迭代算法和基于弱对偶基的比特并行乘法器构成了广泛应用的RS码的译码器。

Straight parallel channel electron multiplier

直平行通道式电子倍增器

Discussed the augment lagrange multiplier algorithm for a class optimal control problems governed by PDEs gave the finite element discretization and its parallel implementation.

讨论了一类由偏微分方程导出的最优控制系统的增广Lagrange乘于算法，给出了有限元逼近及其并行实现算法。

A finite field multiplier architecture is proposed in this paper for ECC. Based on previous digit-serial multiplier architecture, it uses bit-parallel architecture of local parallel to eliminate reduction modulo circuit effectively, and the multiplier architecture also be the same with arbitrary irreducible polynomials.

提出了一种应用于椭圆曲线密码体制中的有限域乘法器结构，基于已有的digit-serial结构乘法器，利用局部并行的bit-parallel结构，有效地省去了模约简电路，使得乘法器适用于任意不可约多项式；

The FPGA hardcore resources were used less as far as possible during the whole system designed, and the multiplier which occupy more resources and had slower speed was not used, parallel input and pipelining technology were used to improve the running speed of circuit.

整个系统设计时都尽量少用FPGA的硬核资源，并且没有使用占用资源多，速度较慢的乘法器的使用，同时还采用了并行输入方式和流水线技术来提高电路的运行速度。