phase lock的例句大全

DSP Based Design of Phase Lock Loop for Digital UPS

基于DSP的数字化UPS锁相设计

The approach can effectively detect the harmonic and reactive currents, and it is no need to adopt the fixed frequency filters and Phase Lock Loo p ( PLL) in it, and not only its circuit configuration is simple, but also to realize it is easily.

该方法能有效地检测出单相电路的谐波电流与基波电流，且不需要采用固定频率的滤波器，不需要锁相环，电路结构简单，易于实现。

PLL ( Phase Lock Loop) technology is employed to realize the frequency tracing and constant phase angle control;

通过采用锁相环技术实现了逆变器工作频率的自动跟踪和容性逆变角度的恒值控制；

the coupling visibilities(cv) of temperature sensor heads were measured with phase lock loop technique.

采用锁相环技术测试了各传感器的分光可见度随温度的变化关系。

The phase-locked loop band-pass filter and the logarithmic amplifier is adopted in the circuit to insure the reliability of receiving signal.

电路中采用锁相带通滤波器和对数放大器，保证有效信号的可靠接收。

The Analysis and Design of the Microwave Phase-locked Frequency Source Used in CDMA Multi-target Telemetering system

CDMA多目标遥测系统用微波锁相本振源的分析与设计

Threshold Analysis of Super-modes of a Diode Laser Array Phase-locked in an External Cavity

外腔锁相二极管激光列阵超模的阈值分析

In this paper, A math model about LTI transfer function of Phase-Locked Loops is introduced, brief discussed trade-offs between the lock time and spur frequency.

文中讨论锁相环线性时不变系统传输函数数学模型，锁相环的锁相时间以及锁相后的扰动毛刺的关系。

A Miniaturized C-Band Latching Phase Shifter Calculation of the Strength of Self-Locking Differential Parts

小型化C波段锁式移相器自锁式差速器的强度计算

Application of Integrated Circuit Phase-locked Loop in Measuring Pulse Duty Factor

IC锁相环在脉冲占空比测量中的应用

5Gb/ s CMOS Monolithic Clock Recovery Circuit Rased on Half-rate Phase-locked Loop

基于半速率锁相环的5Gb/s CMOS单片时钟恢复电路

The new method simplifies the detection circuit as well as improves response speed of the detection algorithm for it does not require phase-locked loop circuit.

该方法不需要锁相环电路，简化了检测电路结构，且提高了检测算法的响应速度。

It uses programmer timing counter producing pulse, lock phase ring controling automatic rise-fall velocity. It realizes preferably working procedure example for making package, fill, seal and cutting off etc. in phase.

该设计采用了可编程定时计数器实现控制脉冲的产生，采用锁相环实现自动升降速的控制，能够实现制袋、下料、封口和切断等工序的同步工作。

The text relates the fundamental principles, structures and designs of phase-locked velocity servo loop for threephase asynchronous motor, and introduces the result of tests.

论述了三相异步电动机锁相式速度控制系统的基本原理、结构及其回路设计。并介绍了研制试验的结果。

Time difference counting method and phase-locked loop technology are adopted. A systematic phase-detection function module is designed. High-precision measurement of the phase difference is achieved. 4.

采用时间差计数法和锁相环技术，设计了系统的鉴相功能模块，实现了相位差的高精度测量。

This paper introduced a system to pick up the bit alignment signal of digital phase-locked loop which is programmed in AHDL language and its CPU is CPLD ( Complicated Programmable Logic Device).

现介绍一种用CPLD复杂可编程逻辑器件为控制核心，采用AHDL语言编程实现数字锁相位同步信号提取的方法。

aiming at the 155mb/ s up-stream velocity of atm-pon system, we design the circuit of the burst-mode optical transmitter. we make the frequency synthesis of the pll ( phase-locked loop) get 155mb/ s clock source.

对于PON系统，针对上行传输速率为155Mb/s时，对突发模式光发射机作了电路设计，在电路设计中采用锁相环频率合成器产生155MHz时钟源系统。

Taking the wharf and water intake project of the third-phase expansion project of Sheyang Power Plant as an example, the authors construct a physical model from Sheyang tide lock to the estuary to do the experiment on current and sediments.

以射阳港电厂三期扩建码头和取水口工程为例，建立射阳闸至河口段物理模型进行水流泥沙试验。

The frame synchronizer was designed based on synchronization state machine using a hard description language, AHDL. To serial data, it possesses functions of dynamic search, verification, and lock of synchronization signal, characterized by self-adaptive phase.

帧同步器采用硬件描述语言AHDL设计，基于同步状态机实现帧同步信号的提取，对串行输入数据具有动态搜索、校验、锁定帧同步信号的功能和自适应相位的特点。

the technology of frequency division phase-locked frequency synthesis is introduced.

介绍分频锁相频率合成技术。