sequential logic的例句大全

And by using the design method of binary sequential logic circuits in MVL field, arbitrary valued sequential logic circuits can be realized with DYL linear And-Or-gates and J-gates as well as MV-D flip-flops.

文中将二值时序电路设计方法推广到多值逻辑系统中，运用DYL电路的线性与或门和阈门以及多值D触发器，实现了任意值数的时序逻辑电路设计。

Design Method of Sequential Logic Circuits Using DT Flip-Flops

应用DT触发器的时序逻辑电路的设计方法

And it is fit for all synchronous sequential logic circuits design.

提出了一种同步时序逻辑电路设计的新方法—次态方程联立法.

A new method of designing synchronous sequential logic circuits is propsed.

提出了一种设计同步时序逻辑电路的新方法.

Application of SPIN in Synchronous Sequential Logic Circuits

SPIN在同步时序逻辑中的应用

With FPGA technique to design sequential logic, the reliability is increased and the debugging becomes easy.

采用FPGA实现喷头时序逻辑，既提高了设计的可靠性，又便于调试。

A Standard Method to Find internal Clock Pulse Overlay Area by Karnaugh Map ── Analysis of Asynchronous Sequential Logic Circuit in the Case or Comples Clock Pulse

利用卡诺图寻找内时钟复盖区的规范方法&复杂时钟下异步时序罗辑电路分析

The methods have useful reference value to using correctly flip-flops and designing sequential logic circuits.

这些方法对于正确使用触发器和设计时序逻辑电路有重要应用参考价值。

A full custom Multiple-function and Multiple-Valued Array Integrated Circuit ( MMAIC) is presented in this paper, which is able to realize binary, ternary combinational logic, sequential logic and multiplexed digital and analog switching function etc.

本文提出了一种可实现二值、三值组合逻辑、时序逻辑和多路数字模拟开关等功能的全定制多功能多值逻辑阵列集成电路（简称MMAIC）。

A threshold memory circuit for realizing arbitrary multivalued sequential logic

一种用于实现任意基数值时序逻辑的阈值存储电路

sequential logic synthesis is an important part of rtl synthesis system design.

时序逻辑综合是RTL综合系统设计中的一个重要部分。

realization of sequential logic synthesis in rtl synthesis system design

RTL综合系统设计中时序逻辑综合的实现方法

Flip-flops are a key component and memory cells of sequential logic circuit.

触发器是构成时序逻辑电路的存储单元和核心部件.

The multiple fault testing of synchronous sequential circuit with the dynamic Boolean equation method which reduces the Exclusive-OR operation to the logic addition one is proposed.

本文提出了同步时序线路多故障测试动态布尔方程方法，它将同步时序线路中的异或运算归结为逻辑加运算，可一次求出被测线上双固定型故障s-a-1和s-a-0的全部测试集。

Firstly, the Ternary Logic Difference is introduced, then a complex model of arbitrary networks is set up on the basis of new ternary algebra, and finally, a new algorithm is presented, by which one can describe the transient process of a sequential circuit completely.

在新三值代数的基础上建立了任意网络的复数模型。最后，本文提出一个新算法，用此算法能完整地描述时序电路的过渡过程。

Based on it, ternary sequential circuits are implemented by using array of universal-logic-module Uks.

在此基础上，利用U k门阵列实现三值时序电路。

It has a logic operation, timing, calculation, sequential control, communications and other functions.

它具有逻辑运算 、 定时 、 计算 、 顺序控制 、 通信等功能.