simulation clock的例句大全

Simulation clock pushing is the key technique in DIS.

仿真时钟的推进是分布交互式仿真系统的关键技术.

Methods The mathematics model and dynamic simulation software-WORKING MODEL 3D were used to build virtual prototype and to simulate the timing characteristics of the clock mechanisms with the unturned escapement in actual environments.

方法把数学模型和动力学仿真软件相结合，模拟真实条件，研究无返回力矩钟表机构的延时特性；

Both instructional and functional simulation for the whole VSP show that this motion estimation coprocessor works correctly with other functional components of VSP under the system clock rate up to 80 MHz.

目前，已经通过VSP芯片整体的指令级与功能级仿真与验证。结果表明，当系统时钟为80MHz时，运动估计协处理器与VSP的其它功能部件及指令部件可以有机协调地工作。

This simulation platform is an instruction level emulator, using instruction queue to simulate the pipeline structure, and analog clock is adapted to simulate the clock cycle of performing an instruction.

该仿真平台是一个指令级仿真器，采用指令队列来模拟流水线结构，并且添加了模拟时钟来模拟每个指令在执行过程中所用的时钟周期。

Time consistency solves the problem of distributed simulation system clock synchronization.

时间一致性需要解决分布式仿真系统中各仿真节点的时钟同步问题。

Calculation for the data resulted from simulation shows that power dissipation of the system adopting DET flip-flop can be reduced evidently because of using the clock with half working frequency, in comparison with its counterpart adopting SET flip-flop.

对模拟所得数据的计算结果表明，与采用相同功能的单边沿触发器的系统比较，由于工作频率减半可使采用双边沿触发器的系统功耗明显降低。

In distributed interactive simulation systems, time/ space coherence is one of the key factors. The time synchronization accuracy between the computers must be reached to some degree, and the time resolution of computer's clock is the main factor that restricts the time synchronization accuracy.

时空一致性是分布交互式仿真的关键问题，联网仿真的计算机之间的的时间同步必须达到一定的精度，而计算机的时钟分辨率是制约仿真系统时间同步精度的重要因素。

Electronic circuit design and simulation tool eda, used to simulate the work and display digital clock.

电子电路设计与仿真工具eda, 用来模拟数码时钟的工作和显示.

Monte Carlo Method Applied to Simulation of Atomic Clock Noise

原子钟噪声的蒙特卡络模拟方法

E1 Circuit Simulation and Clock Synchronization Technology in EPON

EPON系统E1电路仿真及其时钟同步技术

Post simulation waveform has 15.02 ns delay time than system clock edge as add device andwire delay.

在加入了器件延迟与布线延迟后,后仿输出波形对于系统时钟有15.02ns的延迟.

In this paper, a conservative synchronization strategy based on Conservative Time Window ( CTW) is put forward considering the clock synchronization in the process of traffic network distribution simulation.

针对交通网络分布式仿真的时钟同步问题，提出了一种基于时间窗的保守性同步策略。

finite element simulation of microminiature clock mechanism with unturned escapement based on manufacturing characteristics

基于制造特性的微小型钟表机构有限元仿真