wire delay的例句大全

interconnect wire delay questions in deep submicron ic design

深亚微米集成电路设计中的互连线延迟问题

the study and resolution ways of ic interconnect wire delay

集成电路互连延迟问题的研究及对策

The development of traditional processor architecture is restricted by many problems arose in nanometer technology designs, such as power dissipation, wire delay, design complexity, etc. Tiled processor architecture is a potential solution to these challenges.

纳米工艺所带来的功耗、线延迟和设计复杂度等问题制约了处理器体系结构的发展，分片式结构设计是解决这些问题的一种方法。

Tiled Processor Architecture ( TPA), as a many-core architecture design with good scalability, can cope well with challenges such as power consumption, wire delay, design and verification complexity in nano technology.

分片式处理器体系结构（TPA）能够很好地应对纳米工艺代的功耗、线延迟、设计和验证复杂度等一系列问题，是一种具有良好的性能扩展潜力的众核处理器体系结构设计方案。

Passive wire delay, active delay device which can have a delayed effect to signal were studied and utilized as delay units.

能对信号产生延迟作用的无源延迟导线、有源延迟器件等都曾被作为延迟单元被人们研究和利用。

The paper also presents a method to estimate "wire error" in delay measurements.

同时，对测量数据的处理，提出了测量数据有效性判定规则，并提出了一种延迟测量中线路误差的测量方法。

in addition, a heuristic iterative optimization method is well adopted to combine the wire length optimization and path delay optimization.

另外，启发式迭代优化方法很好地统一了以线长优化和路径时延优化为目标的布局算法。