lock loop

DSP Based Design of Phase Lock Loop for Digital UPS

基于DSP的数字化UPS锁相设计

Design of SDH/ SONET Tributary Clock Jitter Attenuation Digital Phase Lock Loop

SDH/SONET支路时钟抖动衰减数字锁相环设计

A improved I p I q detecting method is put forward. In order to select phase A fundamental positive sequence voltage, a voltage selected unit based on low pass filter is used to replace the phase lock loop of I p I q detecting method.

之后提出了一种改进的ip-iq检测法，在该检测法中用基于低通滤波的A相正序电压提取单元代替原ip-iq检测法中的锁相环，以提取A相正序电压。

First modular design the three-phase phase lock loop, which realizes functions of the phase discriminator, loop filter and NCO. With the top connections finished, the whole three-phase PLL design has completed.

首先对三相锁相环进行模块化设计，然后分别实现了鉴相器、环路滤波器和数控振荡器的功能，最后经过顶层连接，完成了整个三相锁相环的设计。

Study of Design Method for Charge Pump Phase Lock Loop

电荷泵锁相环设计方法研究

Timing Acquisition of Impulse Radio System with Orthogonal Analog Phase Lock Loop

脉冲无线电通信系统的正交锁相环路同步方法

The orthogonal analog phase lock loop is used to get the timing information of the impulse radio system and the multi-path component separation.

使用正交模拟锁相环路对无载波的脉冲无线电系统实现多径捕获和同步提取。

Frequency source finally choose the decimal points a VCO frequency and phase lock loop, again through the two times frequency output reached the final index signal.

频率源最后选用了小数分频和压控振荡器构成锁相环路，再通过二次倍频最终输出达到指标的信号。

Relational Digital Phase Lock Loop slot synchronizer for PPM Laser Communication System

PPM光通信相关式数字锁相环时隙同步器