reconfigurable technology

This paper present a design method of IU, which use the reconfigurable technology.

本文提出了一种采用可重组技术设计整数单元的方法.

In this paper, based on the analysis about the reconfiguration of the DES, 3DES and AES, we propose a reconfigurable architecture, which combines reconfiguration technology with pipeline, parallel structure.

本文分析了常用对称密码算法DES、3DES和AES的可重构性，利用流水线、并行处理和可重构技术，提出了一种可重构体系结构。

The work of this thesis is significant to the research of the reconfigurable technology and the development of the important equipment.

论文的工作对新一代网络的构件化可重构技术研究和关键设备研制具有重要意义。

Through update FPGA logic and system software, this platform can support two-dimension code, RFID card and Security control functions, which prove the advantages of SoPC technology& soft/ hardware reconfigurable and platform reuse-able.

另外，通过对升级与更改FPGA硬件逻辑以及系统软件，可使系统平台支持二维条码扫描、RFID卡读写，门禁控制等功能，实现了软硬件体系的可重构与平台的可重用。

Reconfigurable technology based on FPGA using the reconfigurable characteristic of FPGA can sequentially complete different time-discrete logic functions by time division multiplex the logic resource of FPGA.

基于FPGA的可重构技术，就是利用FPGA可以多次重复配置的特点，通过时分复用的方式利用FPGA的逻辑资源，使在时间上离散的逻辑功能在同一FPGA中顺序实现的技术。