高速暂存器
The instruction decoder is designed to facilitate prioritized thread scheduling. The instruction issue logic considers the utilization of the shared execution pipeline. And the interface between direct memory access and scratch-pad memory is refined.
设计了有利于线程优先级调度的译码段,考虑了共享流水线资源利用率的指令发射逻辑和改进的直接存储访问和便签式存储器接口。
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