SDRAM

Image recognition module to complete: for digital image acquisition module control; the SDRAM memory read write control; to complete the uptake of the image recognition, and output quality type information code.

质量检测模块中完成：对图像数据样本发生的控制；对数字样本缓存的读写控制；完成对所摄取的图像识别，并输出代表质量类型的信息码。

The 16 MB SDRAM was the system memory.

16MB SDRAM为系统内存。

This article introduces that in radar raster display system, using SDRAM as video memory and adopting FPGA to carry out the process of control circuit.

本文介绍了在雷达光栅显示系统中，应用SDRAM作为视频存储器时，采用FPGA实现控制电路的过。

The design and verification based on FPGA for integrity of DDR2 SDRAM interface signals

基于FPGA的DDR2SDRAM接口信号完整性设计与验证

The Memory chip is DDR SDRAM memory type chip.

内存芯片的DDR SDRAM内存芯片的类型。

Secondly, we discuss all the function modules of the camera, including power module, start up configuration module, SDRAM and Flash memory module, CPLD logical control module, video capture module, audio transmission module, Ethernet and RS-485 communication module.

第二部分重点讨论了网络摄像机系统各个功能模块的设计，包括电源模块、启动配置模块、SDRAM与Flash存储模块、CPLD逻辑控制模块、视频采集模块、音频传输模块和以太网及RS-485通信模块等。

The embedded system in this thesis include CPU, memory part, LCD part, touching screen, keyboard, FLASH, SDRAM and internet interface and so on.

本论文的嵌入式硬件环境，包括CPU的外围时钟电路，复位电路，存储器单元，LCD模块，触摸屏，键盘，FLASH，SDRAM，网络接口等部分。

Design and Verification of DDR2 SDRAM Controller

DDR2SDRAM控制器的设计与验证

Evaluate the Performance of SDRAM Instruction FIFO Based on Software Model

基于软件模型的SDRAM指令FIFO的性能评估

Then, the thesis designs the video interface module, SDRAM data storage module, FLASH programmer module, PCI communication module and system power module in panoramic camera image compression system in detail.

然后详细介绍了全景摄像机图像压缩系统视频接口模块，SDRAM数据存储模块，FLASH烧写模块，PCI通信模块及系统电源模块的设计方法。

The design of CPLD has adopted the output clock of image sensor to write SDRAM.

CPLD电路设计采用图像传感器的输出时钟触发SDRAM写 过程.

Discusses the FPGA-based image enhance-ment algorithm for hardware implementation and and Image data storage module SDRAM controller design.

论述了基于FPGA的图像增强算法的硬件实现，图像数据存储SDRAM控制器模块的设计。

Compared with the DDR SDRAM, DDR2 SDRAM has higher speed, lower power, higher efficiency and higher stability.

作为第2代DDR存储器的DDR2SDRAM具有高速、低功耗、高密度、高稳定性等特点，在未来的一二年里，它将逐步取代DDR SDRAM而成为内存的主流。

SDRAM access controller design books, contain standard SDRAM readwrite control functions, and auto refresh function.

SDRAM存取控制器设计书, 包含标准的SDRAM读写控制功能, 和自动刷新功能.

RAM comes in many varieties, including dynamic RAM ( DRAM ), synchronous RAM and synchronous dynamic RAM ( SDRAM ).

RAM有多种形式, 包括动态RAM ( DRAM ) 、 同步RAM和同步动态RAM ( SDRAM ).

Use the DSP, extended memory SDRAM and the boot load flash chip, realize a image processing and CPU system.

通过DSP、外扩SDRAM和上电加载FLASH芯片，构建了一个图像处理和中央控制系统。

All memory in the system must have the same primary SDRAM width.

系统中的所有内存必须具有相同的主SDRAM宽度.

DDR2 SDRAM is, at present, one of the most widely used kind of the memory.

DDR2内存是目前应用最为广泛的存储器产品之一。

Modules Design and Verification Technology Research of DDR2 SDRAM Controller

DDR2内存控制器的模块设计和验证平台技术研究

Design and Optimization of SDRAM Memory Interface in High-Definition Video Decoder

高清视频解码芯片中SDRAM存储器接口的设计与优化

Through the high speed DDR SDRAM module at the hardware platform, we may improve the throughput of FPGA digital interface to satisfy the requirement of the high speed D/ A convector for transmission rate of digital interface.

通过硬件平台上的高速DDR SDRAM模块，可以提高FPGA数据端口的吞吐量，满足高速D/A转换器对其数字接口传输速率的要求。

With high-speed, large-capacity storage system design, DDR2 SDRAM offers a more cost-effective solution for designers.

在高速、大容量存储的系统设计中，DDR2SDRAM为设计者提供了高性价比解决方案。

North Bridge is the center of communication with many high-speed buses and connects CPU, SDRAM, APG equipment and PCI equipment.

其中，北桥是整个系统的核心通信部分，含有丰富的高速总线接口，连接了CPU、SDRAM、AGP设备和PCI设备；

Features of DDR SDRAM, basic configuration and timing of DDR controller, together with basic configuration and timing of PCI bus, are discussed first, while basic theory and development process of FPGA are introduced.

论文中首先讨论了DDR SDRAM的特性，DDR控制器的基本结构和时序，以及PCI总线的基本结构和时序，并介绍了FPGA的基本原理和开发过程。

DDR SDRAM memory bank is used as the mass buffer in some applications.

本处理板中还加入了一个DDR SDRAM内存条，主要是考虑到实际应用中可能需要大容量缓存。

Design of Mass Storage Based on USB 2.0 Protocol and SDRAM

基于USB2.0及SDRAM的大容量存储卡设计

Complete the establishment of debugging environment, CPU starting up and reset control words reading, SDRAM testing, NOR Flash testing, serial debugging and network module debugging gradually.U-Boot porting.

建立调试环境，逐步完成了CPU的启动及复位控制字的读取、SDRAM的测试、Nor flash的测试、串口的调试和网络模块的调试。U-Boot移植。

A digital audio recording, storing and playing system based on FPGA includes the processing of audio signals, the access to SDRAM and the display on LCD ( character).

基于FPGA的数字音频采集、存储和播放系统实现了数字音频信号的处理、SDRAM存取以及字符型LCD显示等功能。

Design and realization of high speed and deep asynchronous FIFO based on DDR2 SDRAM

基于DDR2SDRAM的高速大容量异步FIFO的设计与实现

A design is expatiated which can satisfy the speed and capacity of the memory only using normal DDR ( Double Date Rate) SDRAM. And implemented the DDR memory controller in FPGA.

阐述了一种采用普通DDR内存即可实现的高速大容量报文缓存方案，并在FPGA中实现了DDR内存接口管理控制器。