logic circuit的例句大全

Using Programmable Logic Devices to Develop a High-Density Integrated Logic Circuit

用可编程逻辑器件开发高集成度的逻辑电路

Logic Circuit Level Design by Using MDS Diagram& "A 30's basketball Timer" Design

应用MDS图的逻辑电路级设计&篮球30秒定时计时器的设计

Improvement of Back Logic Circuit of IC Test System and Research of Analog Delay Line Capability

集成电路测试系统后逻辑支持电路改进与模拟延迟线性能分析

A Standard Method to Find internal Clock Pulse Overlay Area by Karnaugh Map ── Analysis of Asynchronous Sequential Logic Circuit in the Case or Comples Clock Pulse

利用卡诺图寻找内时钟复盖区的规范方法&复杂时钟下异步时序罗辑电路分析

Microcomputer can be used to implement the switchover functions of k-type logic circuit.

能使用微计算机实现K结构电路拉辑功能切换等等。

The dummy digital logic circuit lab based on WEB

基于Web的数字逻辑电路虚拟实验室

It integrated flip-latch, coding unit, data bus, frequency division unit, logical compare unit, counter and logic circuit into a single CPLD chip, and dramatically decreased PCB's area and increased system reliability.

在一片CPLD中集成了低位地址锁存、地址译码、数据总线、分频电路、比较、记数以及逻辑电路等。

The hardware circuit includes the aspects like collecting circuit, extended memory circuit, CPLD internal logic circuit, power supply and reset circuit.

系统的硬件电路包括图像采集电路、存储器扩展电路、CPLD内部逻辑电路、电源和复位电路等功能模块。

consequently, the studied device shows a good potential for multiple-valued logic circuit applications.

因此，本研究元件极适合于多值邏辑电路应用。

The test pattern generation algorithms for combinational logic circuit and the fault types were discussed.

讨论了组合逻辑电路的故障诊断的方法，故障的类型。

Analysis of a symmetrical ternary logic circuit by means of truth matrix

对称三值逻辑电路的真值矩阵分析法

A special testing sequence input is need for measuring maximum dyna-mic current of a combinational logic circuit.

组合逻辑电路的最大动态电流测试应在电路的原始输入端施加一个特定的测试序列才能实现。

The Development of CMOS Symmetrical Ternary Logic Circuit

对称三进制逻辑CMOS电路的试制

Graph approach for logic circuit input is adopted by the DCLSS, device model is based on five-value, three-strength, and up/ down-jump delay model, simulation algorithm is on table-event method, time-mapping technique, and hybrid simulation of gate and function block level.

软件采用图形输入方式，元件模型为五值、三强度及上下跳变延迟，模拟算法采用表驱动方法、时间映射方式、门级和功能级混合模拟。

Application of First Degree Boolean Difference for Test Generation of Combinational Logic Circuit

一阶布尔差分在组合逻辑电路测试生成中的应用

The digital part includes closed loop oscillator, frequency divider, combinational logic circuit, non-overlapping clock generation circuit.

数字部分包含环形振荡器、分频器、组合逻辑门、非交叠时钟产生电路。

A CMOS symmetrical three-valued ternary logic circuit was designed and fabricated, based on the information associated with symmetrical ternary logic combined with CMOS circuit processing features.

根据有关对称三进制逻辑的资料，结合CMOS电路生产工艺特点，设计并试制了对称三值逻辑CMOS系列电路。

The Logic Circuit Design of Deka-Value Threshold Gate and T-Gate

十值阈门和T门电路的研究

Application of truth matrix to analyze a logic circuit is intuitive and simple, and the results may lead to the derivation of some identical relations of certain symmetrical ternary logic system.

应用真值矩阵分析逻辑电路具有直观、简便的优点，并可由其运算结果导出一些对称三值逻辑运算的恒等式。

The RTD has a room temperature peak-to-valley ratio of 5.2 ∶ 1 with a peak current density of 22.5kA/cm2.The HEMT has a 1 μ m gate length with a-1V threshold voltage. A logic circuit called a monostable-to-bistable transition logic element ( MOBILE) circuit is developed.

RTD室温下的峰谷电流比为5.2∶1，峰值电流密度为22.5kA/cm2.HEMT采用1μm栅长，阈值电压为-1V.设计电路称为单稳态-双稳态转换逻辑单元（MOBILE）。