logic circuit

Analysis of a symmetrical ternary logic circuit by means of truth matrix

对称三值逻辑电路的真值矩阵分析法

Investigation into Ternary GaAs Logic Level Circuit s

三值GaAs逻辑级电路的研究

The author depicts the necessity of adopting ternary logic in fault detection, with detailed introduction of the structure and operation principle for ternary logic fault detection circuit.

闸明了应用三值逻辑进行故障检测的必要性，较详细地介绍了三值逻辑故障检测电路的结构和工作原理。

Application of truth matrix to analyze a logic circuit is intuitive and simple, and the results may lead to the derivation of some identical relations of certain symmetrical ternary logic system.

应用真值矩阵分析逻辑电路具有直观、简便的优点，并可由其运算结果导出一些对称三值逻辑运算的恒等式。

The number of inputs available to a given logic circuit.

通常是“逻辑电路”的简写.

A CMOS symmetrical three-valued ternary logic circuit was designed and fabricated, based on the information associated with symmetrical ternary logic combined with CMOS circuit processing features.

根据有关对称三进制逻辑的资料，结合CMOS电路生产工艺特点，设计并试制了对称三值逻辑CMOS系列电路。

Experimental results have demonstrated the basic ternary logic functions: complement, minimum, maximum, cycle and literals. A circuit design of ternary T-gate or triplexer has also been proposed.

实验上演示了补、与、或、循环和阈等基本的三值逻辑函数，并给出了三路选择开关线路的设计。

Test Generation of Digital Circuit Logic Test System

数字电路逻辑测试系统中的测试生成

The hardware circuit includes the aspects like collecting circuit, extended memory circuit, CPLD internal logic circuit, power supply and reset circuit.

系统的硬件电路包括图像采集电路、存储器扩展电路、CPLD内部逻辑电路、电源和复位电路等功能模块。

To avoid this circumstance, this paper puts forward a method for normalizing Haar function and judging dangerous appearance in combination logic circuit by use of ha coefficient map under the condition of variable number < 6. This method has the characteristics of being simple and direct.

为避免这种现象，给出了Haar函数归一化的一种方法以及在变量数<6时用ha系数图判断组合逻辑电路险象的方法，该方法具有简单、直观的特点。

The level of complexity in testing the designed logic circuit and system.

对所设计的逻辑电路和系统进行故障测试的难易程度.

The Development of CMOS Symmetrical Ternary Logic Circuit

对称三进制逻辑CMOS电路的试制

Therefore, the studied devices provide a promise for signal amplifier and logic circuit applications.

因此, 此元件亦拥有了电晶体放大功能又具备负微分电阻特性,并提供了逻辑电路上之应用.

A Simplified Design of a Mixed Level I~ 2L Three Valued Logic Circuit

混合级I~2L三值逻辑电路的简化设计

The digital part includes closed loop oscillator, frequency divider, combinational logic circuit, non-overlapping clock generation circuit.

数字部分包含环形振荡器、分频器、组合逻辑门、非交叠时钟产生电路。

Improvement of Back Logic Circuit of IC Test System and Research of Analog Delay Line Capability

集成电路测试系统后逻辑支持电路改进与模拟延迟线性能分析

The test pattern generation algorithms for combinational logic circuit and the fault types were discussed.

讨论了组合逻辑电路的故障诊断的方法，故障的类型。

A logic circuit that produces an output inverse to that of an OR gate.

或非门,反或门:逻辑原件,产生输出端转变到“或”门.

The dummy digital logic circuit lab based on WEB

基于Web的数字逻辑电路虚拟实验室

An inverter is logic circuit that has one input and one output.

门是至少具有两个输入(端)和?个输出(端)的逻辑毛路.

The telecom enterprise is different from general enterprises which produce goods. It provides fictitious service for consumers with sound and data, which need various facilities, including logic circuit, drive, electrical wire and network resource.

电信运营企业与一般生产型企业不同，它通过提供语音、数据等业务为用户提供虚拟服务，这种服务依靠企业所拥有的各种设备、逻辑电路、动力、管线等综合网络资源共同提供。

Application of First Degree Boolean Difference for Test Generation of Combinational Logic Circuit

一阶布尔差分在组合逻辑电路测试生成中的应用

A special testing sequence input is need for measuring maximum dyna-mic current of a combinational logic circuit.

组合逻辑电路的最大动态电流测试应在电路的原始输入端施加一个特定的测试序列才能实现。

This course will provide an introduction to computer architectures from logic circuit design to software design.

这门课将介绍电脑的组织架构从逻辑电路层到软体运用层.

This kind of function fine tri-state logic indicating circuit is composed of 555 integrate timer, logical level threshold value adjustment circuit and the logic indicating circuit.

这种功能优良的三态逻辑指示电路由555IC集成定时器、逻辑电平阈值调节设定电路、逻辑指示电路构成。

Logic Circuit Level Design by Using MDS Diagram& "A 30's basketball Timer" Design

应用MDS图的逻辑电路级设计&篮球30秒定时计时器的设计

The thesis offers APD signal amplify circuit chart and controlling time-series logic circuit principle chart bearingvalue.

给出了APD信号放大电路和控制时序逻辑电路原理图.

The Logic Circuit Design of Deka-Value Threshold Gate and T-Gate

十值阈门和T门电路的研究

The RTD has a room temperature peak-to-valley ratio of 5.2 ∶ 1 with a peak current density of 22.5kA/cm2.The HEMT has a 1 μ m gate length with a-1V threshold voltage. A logic circuit called a monostable-to-bistable transition logic element ( MOBILE) circuit is developed.

RTD室温下的峰谷电流比为5.2∶1，峰值电流密度为22.5kA/cm2.HEMT采用1μm栅长，阈值电压为-1V.设计电路称为单稳态-双稳态转换逻辑单元（MOBILE）。

Working frequency is from 50 Hz to 5 kHz . Measuring function and range change arecontrolled by logic circuit.

工作频率为50赫至5千赫.